As?a?Sr.?Analog?Design?Engineer?,?you?will?have?the?opportunity?to?utilize?your?analog/mixed?signal?skills?to?design,?simulate?and?provide?support?for?various?high?accuracy?analog/mixed?signal?blocks?developed?for?our?proprietary?technology.?You?will?have?the?opportunity?to?be?exposed?and?to?work?with?a?highly?enthusiastic?engineering?team.
Experience
Theoretical?and?practical?understanding?of?analog?circuits?suitable?for?designing?in?CMOS?processes?as?well?as?device?physics?and?control?theory
Experience?in?designing?opamps,?comparators,?current?mirrors,?active-loads,?voltage?regulators,?LDOs,?charge?pumps?–?must?have
Familiarity?in?designing?configurable?PTAT?references?(bandgap?and?current?references)?–?must?have
Familiarity?with?any?non-volatile?process?technologies?such?as?EEPROM?or?Flash?is?a?plus
Fabrication?process?variation?impacts?and?performance,?Monte?Carlo?sampling?–?must?have
Silicon?debug?experience?–?desirable
Initiative,?innovation,?good?communication?and?team?pla
Floor?planning?for?analog?layout?blocks
EDA?tools?including?the?Cadence?and/or?Mentor?Graphics?design?fr
Linux/Unix?platforms
Requirements
5+?years?of?analog/mixed-signal?integrated?circuit?design
MSEE?preferred
Good?verbal?and?writing?communication?skills
Self?motivated
該崗位可定位在上海拍字節(jié)微電子有限公司或者無錫拍字節(jié)科技有限公司
更新于 2026-04-01
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Job Description
Work with Front-End design team physical design team fsuper large-scale SoC chip physical implementation from RTL to GDS. Focus on physical design of deep sub-micron ultra large chip including block chip level synthesis, floorplan, place route, timing closure, physical verification, EM/IR signoff checks etc. The individual is expected to be an expert in multiple aspects in PD areas provide technically leadership to the engineering team.
Job Requirement
1. Hands on experience in super large-scale SoC chip physical design, especially experience in 7nm FinFet technology high-speed design implementation.
2. Solid knowledge rich experience on synthesis, floorplan, place, CTS routing, static timing analysis, EM/IR-drop physical verification.
3. Project experience on hierarchical flow such as top-level partition, timing budgeting, pin assignment Power Network Planning etc
4. Expertise with Synopsys/Cadence/MentEDA tools
5. Familiar with Unix/Linux environment good at scripts
6. A high-level of self-motivation a proactive approach to solving problems.
7. Good communication skills, strong interpersonal skills the flexibility
8. Dedicated, hardworking, good team player
更新于 2025-12-26
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