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analog design engineer

design engineer

As?a?Sr.?Analog?Design?Engineer?,?you?will?have?the?opportunity?to?utilize?your?analog/mixed?signal?skills?to?design,?simulate?and?provide?support?for?various?high?accuracy?analog/mixed?signal?blocks?developed?for?our?proprietary?technology.?You?will?have?the?opportunity?to?be?exposed?and?to?work?with?a?highly?enthusiastic?engineering?team.
Experience
Theoretical?and?practical?understanding?of?analog?circuits?suitable?for?designing?in?CMOS?processes?as?well?as?device?physics?and?control?theory
Experience?in?designing?opamps,?comparators,?current?mirrors,?active-loads,?voltage?regulators,?LDOs,?charge?pumps?–?must?have
Familiarity?in?designing?configurable?PTAT?references?(bandgap?and?current?references)?–?must?have
Familiarity?with?any?non-volatile?process?technologies?such?as?EEPROM?or?Flash?is?a?plus
Fabrication?process?variation?impacts?and?performance,?Monte?Carlo?sampling?–?must?have
Silicon?debug?experience?–?desirable
Initiative,?innovation,?good?communication?and?team?pla
Floor?planning?for?analog?layout?blocks
EDA?tools?including?the?Cadence?and/or?Mentor?Graphics?design?fr
Linux/Unix?platforms
Requirements
5+?years?of?analog/mixed-signal?integrated?circuit?design
MSEE?preferred
Good?verbal?and?writing?communication?skills
Self?motivated
該崗位可定位在上海拍字節(jié)微電子有限公司或者無錫拍字節(jié)科技有限公司
更新于 2026-04-01
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Our offer · ? 10 days annual leave fnew employees · ? Business trip accommodation in 4-5 stars hotel high business trip allowance · ? Overtime payment according to Chinese law · ? 12% household fund rate · ? 8 hours per day 5 working days per week · ? Further training possibilities within the group of companies in Austria ·Corporate events · ? Willingness to overpay depending on specific work experience qualifications Your tasks · ? Design detail engineering of automation machinery · ? Preparation of detail assembly drawings · ? Preparation of corresponding bills of materials · ? Accompanying support fassembly start-up work · ? Preparation of cycle time analyses fthe program sequence · ? Preparation of equipment lists fselecting the hardware · ? Complete the other tasks assigned by superi· ? Project responsibilities · ? Project Concept preparation, ? Project planning · ? Coordination of interfaces
Your profile · ? Solid education (BachelMaster) in the field of mechanical engineering · ? Good commof English is required · ? Readiness to travel within China · ? Sound experience in the field of project management · ? Interest on complex technical commercial tasks · ? Service-oriented attitude excellent customer handling · ? Ability to communicate to work in a team · ? Ability to assert yourself to make decisions · ? Readiness to take on responsibility
更新于 2026-03-01
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工資待遇區(qū)別

崗位名稱
平均工資
較上年
¥19.2K
--
說明:analog design engineer和design engineer哪個(gè)工資高?analog design engineer高于design engineer。analog design engineer平均工資¥35.6K/月,2026年工資¥K,design engineer平均工資¥19.2K/月,2026年工資¥K,統(tǒng)計(jì)依賴于各大平臺(tái)發(fā)布的公開數(shù)據(jù),系統(tǒng)穩(wěn)定性會(huì)影響客觀性,僅供參考。

就業(yè)前景區(qū)別(歷年招聘趨勢(shì))

崗位名稱
2025年職位量
較2024年
說明:analog design engineer和design engineer哪個(gè)就業(yè)前景好?analog design engineer2025年招聘職位量 13,較2024年增長(zhǎng)了 44%。design engineer2025年招聘職位量 92,較2024年增長(zhǎng)了 16%。統(tǒng)計(jì)依賴于各大平臺(tái)發(fā)布的公開數(shù)據(jù),系統(tǒng)穩(wěn)定性會(huì)影響客觀性,僅供參考。

學(xué)歷要求區(qū)別

碩士 87.5%
本科 12.5%
本科 80.6%
不限學(xué)歷 8.3%
大專 5.6%
碩士 5.6%
說明:analog design engineer和design engineer的區(qū)別? analog design engineer需要什么學(xué)歷?碩士占87.5%,本科占12.5%。 design engineer需要什么學(xué)歷?本科占80.6%,不限學(xué)歷占8.3%,大專占5.6%,碩士占5.6%。

經(jīng)驗(yàn)要求區(qū)別

1-3年 37.5%
3-5年 37.5%
不限經(jīng)驗(yàn) 25.0%
3-5年 41.7%
5-10年 19.4%
不限經(jīng)驗(yàn) 19.4%
1-3年 16.7%
應(yīng)屆畢業(yè)生 2.8%
說明:analog design engineer和design engineer的區(qū)別? analog design engineer經(jīng)驗(yàn)要求哪個(gè)最多?1-3年占37.5%,3-5年占37.5%,不限經(jīng)驗(yàn)占25.0%。 design engineer經(jīng)驗(yàn)要求哪個(gè)最多?3-5年占41.7%,5-10年占19.4%,不限經(jīng)驗(yàn)占19.4%,1-3年占16.7%,應(yīng)屆畢業(yè)生占2.8%。

design engineer與其他崗位進(jìn)行PK